Truefy Technologies has different engagement models, from consulting to Final delivery of chips. We provide consulting services in all ASIC Design domains.

Truefy Technologies team expertise in Design Implementation encompasses flows/methodologies from front-end to the back-end. The core-skills include RTL Design, Verification, RTL Synthesis, Timing Analysis, DFT, Formal Verification, Physical Design Closure (Floor planning, Clock Tree Synthesis, P&R, Timing, Noise, Power & IR-Drop/Electro migration Analysis and Physical Verification).

The services in Design Implementation encompass complete RTL to GDSII implementation in Synopsys & Cadence flows in 32nm, 45nm, 65nm, 90nm, 130nm.

Truefy Technologies has credentials in working on Physical Design expertise across complex blocks and has experience with timing closure on flat as well as hierarchical designs.

We have a successfully executed turn key projects – Spec to Tested Chips, Consultation services we have right from RTL design to Finished chips. We have good relations with multiple Semiconductor fabs, can give you cost effective solution.

Design

• • • Architectural Design Implementation
    • Spec Development RTL, Implementation (SV, Verilog, VHDL,) & Simulation.
    • Synthesis
  • Timing

• Verification

Full Custom Activity (AMS)

• STD cell, I/O development & verification
• Custom layout and Physical Verification
• Extraction
• Characterization, Spice Simulation
• Different models / View generation

Implementation

•  Synthesis / STA
•  Physical Design
•  Floorplan
•  Clock distribution (CTS, HTree etc) and analysis
•  Scan rest itching (check formatting matches with remaining data)
•  Place & Route
•  Timing closure
•  DFM
•  Physical verification (DRC/LVS)